FIGS. 1 and 2 are, respectively, two generalized, simplified top and sectioned side views of a portion of a strained channel semiconductor device such as a MOSFET 10 according to the prior art. FIG. 2 is taken along line 2—2 of FIG. 1.
MOSFET 10 comprises a generally planar semiconductor substrate 12, on which may be designated an array or matrix of substrate segments 14, only one of which is shown in FIGS. 1 and 2. The substrate 12 may be a body of bulk semiconductor or a layer of semiconductor on an insulative layer (“SOI”). Typically, the substrate 12 is silicon, though other semiconductors are contemplated.
A MOSFET 10 may be fabricated on and in each segment 14. Each MOSFET 10 includes a source 16 and a drain 18 formed in the semiconductor segment 14 on either side of a gate 20. The gate 20 comprises a gate dielectric 22 insulating a gate electrode 24 from the semiconductor segment 14 and from portions of the source 16 and the drain 18 that may extend under the gate 20.
An active area 26 of the semiconductor segment 14 is defined or delineated by the inner boundary 28 of an electrically insulative material 30 filling a shallow trench 32 that surrounds the active area 26. The combination of the trench 32 and the insulative material 30 is typically referred to as STI, or shallow trench isolation 30/32. Note that the depth of the “shallow” trench isolation can have a wide range, e.g., 0.3–1.0 μm in the current generation of 0.13 μm CMOS or bipolar technology, depending on the process etching capability and the level of electrical isolation needed.
The active area 26 has a length L between two opposed termini 34 and 36 that coincide with opposed portions of the inner boundary 28. The active area 26 also has a width W that is normal to the length L between two opposed sides 38 and 40 that coincide with opposed portions of the inner boundary 28. Thus, the active area 26 is defined by the product L*W and has a periphery made up of the termini 34, 36 and the sides 38, 40. Orthogonal X, Y axes are shown in FIG. 1. The length L of the active area 26 lies along the X-axis; the width W lies along the Y-axis.
Between the source 16 and the drain 18 in the segment 14 there is defined a channel 42 within the active area 26. Conduction selectively occurs or is prevented within the channel 42 and between the source 16 and the drain 18 depending on electrical signals applied to the gate electrode 24, as is well known.
The channel 42 has an effective channel length LE between the facing extremities of the source 16 and the drain 18, which is slightly shorter than the so-called “printed length” LP, which is roughly equal to the physical length of the gate 20. The effective length LE lies along the X-axis. The width of the channel 42 is roughly equal to the width W of the active area 26 along the Y-axis. The direction of current flow in channel 42, evidenced by the movement of electrons and holes, between source 16 and drain 18 is generally along the X-axis or the effective length LE of the channel 42.
It is known that uni-axial mechanical tensile or compressive stress in the channel 42 along the X-axis, as well as the X component of bi-axial mechanical X,Y stress in the channel 42, increases or decreases the mobility of carriers, electrons and holes in the channel 42 and thereby also increases or decreases saturation velocity. Mechanical stress along or lengthwise of the channel 42 with desirable polarity (i.e., tensile or compressive) that increases carrier mobility in the channel 42 generally will increase the magnitude of the drive current of the MOSFET 10.
More specifically, it is known that producing or increasing tensile stress—or eliminating or reducing compressive stress—along the channel 42 increases electron mobility in n-MOS devices. Producing or increasing compressive stress—or eliminating or reducing tensile stress—along the channel 42 increases hole mobility in p-MOS devices.
It is also known that mechanical compressive stress along the Y-axis, across the channel 42, can retard or decrease the diffusion along the X-axis of deleterious impurities into the channel 42. Such impurities may be either an intended (e.g., by source and drain implantation), or an unintended but inherent, result of certain processing steps (e.g., metal atoms diffusing during silicide formation) associated with the fabrication of the MOSFET 10. Mechanical stress along the Y-axis and across or widthwise of the channel 42 does not appear to significantly affect carrier mobility along the channel 42 in the X-axis between the source 16 and the drain 18.
Even if the MOSFET 10 is fabricated without any attempt being made to generate or affect stress in the channel 42, a certain amount of residual mechanical stress nonetheless exists in the channel 42 due to the presence of the STI 30/32. For example, when fabricating the MOSFET 10 in a silicon substrate 10, the trench 32 may be filled with an insulative material 30 such as SiO2 deposited by high-density plasma (“HDP”) chemical vapor-deposition (“CVD”). Insulative material 30 deposited in this manner has a lower coefficient of thermal expansion than the segment 14 of the silicon substrate 12, resulting in residual bi-axial (X, Y) compressive stress in the active area 26. As the size of the active area 26 is reduced pursuant to current trends in CMOS technology, this residual compressive stress increases significantly. The compressive bi-axial stress typically is not symmetrical (e.g., may be higher in the X direction or along the length L of the channel 42 than in the Y direction along the width W of the channel 42 if the length L is smaller than the width W). The residual mechanical compressive stress also typically is not uniform in either direction (e.g., decreasing from the termini 34, 36 and the sides 38, 40 of the active area 26 towards its central regions).
If the STI 30/32 includes an insulative material 30 having a higher thermal expansion coefficient than the segment 14 of the substrate 12—or if the material 30 is porous and shrinks inward following fabrication of the MOSFET 10—the residual mechanical stress along and across the channel 42 is tensile. Other than being tensile, the foregoing comments regarding residual compressive stress in the channel apply. In the following embodiment, it will be assumed that the STI 30/32 includes material most popularly formed by the HDP CVD method and having a lower thermal expansion coefficient than the substrate, and that the residual stress in the active area is compressive.
Mechanical stress along the channel 42 can be intentionally increased or decreased in the X direction through the use of a highly stressed SiN (Si3N4) etch stop layer (not shown) that is typically applied atop the gate 20 and to other portions of the in-process MOSFET 10 in the course of forming electrical contacts (not shown) to the source 16 and the drain 18. The total stress along the channel 42 is then the result of superimposing the compressive or tensile component of the stress imposed by the SiN layer on the residual stress imposed by the STI 30/32.
It is known generally that if the SiN layer is formed by plasma-enhanced chemical-vapor deposition (“PECVD”), the stress component imposed by the layer on the channel 42 is compressive, which is added to and either increases or reduces the residual stress imposed by the STI 30/32 along the channel 42. If the SiN layer is formed by thermal chemical vapor deposition (“TCVD”), a tensile stress component is imposed along the channel 42 and is added to the STI 30/32-imposed residual stress along the channel 42.
Concerning the SiN layer, if the residual stress along the channel 42 is compressive and the SiN layer is formed by PECVD, the increase in compressive stress along the channel 42 will result in enhancement of hole mobility in p-MOS devices, but will degrade electron mobility in n-MOS devices. If the residual stress along the channel 42 is compressive and the SiN layer is formed by TCVD, the decrease in or elimination of compressive stress along the channel 42 enhances electron mobility in n-MOS devices but degrades hole mobility in p-MOS devices. Similarly, if the residual stress along the channel 42 due to the STI 30/32 is tensile, a PECVD SiN layer will reduce this tensile stress, while a TCVD SiN layer will increase the residual tensile stress.
Ion implantation of Ge into the SiN layer relaxes the stress in the layer, resulting in the addition of less stress, compressive or tensile, to the residual compressive stress along the channel 42. Implantation of Ge into only selected portions of the SiN layer results in its additive stress being applied only where desired.
Another technique for affecting the stress in the channel 42 selectively relates to the gate electrode 24. Typically, the gate electrode 24 is initially formed of CVD polysilicon. Thereafter, the polysilicon gate electrode 24 is subjected to Co (or Ti) siliciding to lower its sheet resistivity. If certain n-type dopants with relatively large atoms (compared to a silicon atom), such as As, are selectively implanted into the silicide of n-MOS gate 20, and the gate 20 is thereafter annealed with an SiO2 cap layer thereon, the gate 20 is in tensile stress due to large As atoms in silicided poly-silicon gate 20, thus inducing or adding tensile stress to the residual stress along the channel 42 for higher electron mobility in n-MOS. Therefore, using such selective As implantation into an n-MOS gate only, the electron mobility in the n-MOS gate is enhanced, so as to not adversely affect hole mobility in a p-MOS.
While both the selective implantation of Ge into the SiN contact etch-stop layer and implantation of As into the silicided gate electrode 24 are compatible with typical CMOS processes, they involve complicated additional steps to MOSFET fabrication and add cost to the MOSFET 10.